The first RISC-V portable computer is now available
The DevTerm R-01 is a RISC-V based "slabtop" computer.
The DevTerm, from Clockwork, is a “slabtop” computer that I have lusted after for quite some time.
With a form factor inspired by the legendary TRS-80 Model 100 “slab” style computer, it’s hard to not immediately fall head over heels for this adorable little computer.
Well. Today, the Clockwork team has announced something I want even more… a DevTerm powered by a RISC-V CPU.
Here’s what’s included for the $239 list price:
ClockworkPi v3.14 mainboard
R-01 Core module (RISC-V 64bit Single-core RV64IMAFDCVU @ 1.0GHz, No GPU, 1GB DDR3)
Ext. module
6.86-inch IPS screen module
Clockwork 65% keyboard
Battery module*
Dual speaker
58mm 200dpi thermal printer component
Shells and bracket system
32GB high-speed TF-card with clockworkOS
Worth noting that the RISC-V model contains significantly less RAM than the ARM-based versions of the DevTerm (1 GB, compared to 2 or 4 GB for ARM). And, as this is the first real “laptop adjacent” computer running a RISC-V processor… there are bound to be some hiccups.
The Clockwork team makes this disclaimer:
DevTerm R-01 is a highly experimental model and requires some experience with Linux system & FOSS. We strongly recommend all beginners to choose other models.
But, you know what? That just makes me want it all the more.
To be among the first to use an open source, RISC-V CPU in a regular computer? A portable one, no less?! To be a pioneer of a more open hardware future? That sounds like an absolute privilege.
The RISC-V DevTerm looks like pure fun and joy. What computing should be.
Now to see if I can convince my wife to let me buy one.
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I, umm, impulse bought this. The ARM ones had little appeal to me other than the form factor as I have several ARM computers already. But, a reasonably priced RISC-V machine and a cool form factor? Yes please. Without a GPU it will be a text based machine, similar to the TRS-80 from which it draws inspiration, but it should be more than sufficient for SSH and telnet.
EDIT: This chip is beefier than I thought it would be. I had multiple comments on this, and finally found the datasheet from Allwinner and what follows is what I found.
**Allwinner D1 SOC facts in brief:**
* XuanTie C906 RISC-V CPU and HiFi4 DSP
* DDR2/DDR3 SDRAM
* SD3.0/SDIO3.0/eMMC5.0
* H.265/H.264/MPEG-1/2/4/JPEG/VC1 decoding, up to 4K
* JPEG/MJPEG encoding, up to 1080p@60fps
* Allwinner SmartColor2.0 post processing
* Supports de-interlace (DI) up to 1080p@60fps
* Supports Graphic 2D (G2D) hardware accelerator including rotate, mixer, LBC decompression functions
* RGB interface up to 1920 x 1080@60fps
* Dual link LVDS interface up to 1920 x 1080@60fps 4-lane MIPI DSI up to 1920 x 1200@60fps
* HDMI TX interface up to 4K@30fps
* CVBS OUT interface, supporting NTSC and PAL format
* 8-bit parallel CSI interface
* CVBS IN interface, supporting NTSC and PAL format
* 2 DACs and 3 ADCs
* LINEOUTLP/N, LINEOUTRP/N, HPOUTL/R, MICIN1P/1N, MICIN2P/2N, MICIN3P/3N, LINEINL/R, FMINL/R
* Three I2S/PCM external interfaces (I2S0, I2S1, I2S2)
* Maximum 8 digital PDM microphones (DMIC)
* OWA TX and OWA RX, compliance with S/PDIF interface
* AES, DES, 3DES, RSA, MD5, SHA, HMAC
* Integrated 2 Kbits OTP storage space
* USB 2.0 DRD (USB0) and USB 2.0 HOST (USB1)
* 10/100/1000 Mbps Ethernet port with RGMII and RMII interfaces
* Up to 6 UART controllers (UART0, UART1, UART2, UART3, UART4, UART5)
* Up to 2 SPI controllers (SPI0, SPI1)
* Up to 4 TWI controllers (TWI0, TWI1, TWI2, TWI3)
* CIR RX and CIR TX
* 8 independent PWM channels (PWM0 to PWM7)
* 2-ch GPADC
* 4-ch TPADC
* 1-ch LRADC
* LEDC
Still waiting for mine :( I hope they manage to get these out.